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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Eric LaForest‏ @elaforest 1 Aug 2017
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      Eric LaForest Retweeted Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

      Likely not. But that example is a particular subtlety of simulation I never noticed! I have to go fix my simulation harness now... :Phttps://twitter.com/oe1cxw/status/892345863254794241 …

      Eric LaForest added,

      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩 @oe1cxw
      Current Status. I admit this can all be very confusing for a beginner. But should I really spend hours of my time giving those answers? pic.twitter.com/cHA6Wm9b17
      2 replies 3 retweets 2 likes
    2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 1 Aug 2017
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      Replying to @elaforest

      Clock edges at timestamp 0 are especially tricky. I've even seen simulators "optimize away" those edges in some cases (in violation of LRM).

      1 reply 0 retweets 0 likes
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 1 Aug 2017
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      Replying to @oe1cxw @elaforest

      This code with Icarus Verilog: no output. (bug imo) Same code with xsim and modelsim: "ping" Verilator: Did you run with --x-initial-edge?pic.twitter.com/8Z5hiRCWuq

      1 reply 0 retweets 1 like
    4. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 1 Aug 2017
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      Replying to @oe1cxw @elaforest

      JFYI, I've now reported the bug in Icarus Verilog: https://github.com/steveicarus/iverilog/issues/160 …

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 1 Aug 2017
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      Replying to @oe1cxw @elaforest

      Oh yeah, that's a race as well: Sim can decide to schedule head of always block (empty block before @(..)) before scheduling the >>

      9:44 AM - 1 Aug 2017
      1 reply 0 retweets 0 likes
        1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 1 Aug 2017
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          Replying to @oe1cxw @elaforest

          initial assignment for clk. Then the always block reaches the @(...) only after the initial clock edge has been propagated.

          0 replies 0 retweets 0 likes
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