Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

What? Is the ordering between declaring a reg and always blocks undefined? Sounds fishy, but haven't checked LRM

Afaik initializations add events directly to the active event queue. So yes, I think this is a race condition.

You can check the "scheduling semantics" chapter of the LRM.. But whenever I do that I end up being more confused afterwards.. :)

3.2.2 says reg decl with val should be treated "as if the assignment occurred in a blocking assignment in an initial construct" ...

Which LRM are you reading? IEEE-1364-2005 3.2 is about whitespaces, IEEE-1800-2009 3.2 is about "design elements" (modules, checker, ..).

Neither has a section 3.2.2. But you are right: init value is like initial block. Don't need to check LRM for that.

But this is not the question: The question is if in the Verilog stratified event queue model it is guaranteed that an always block >>