Current Status. I admit this can all be very confusing for a beginner. But should I really spend hours of my time giving those answers?pic.twitter.com/cHA6Wm9b17
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But this is not the question: The question is if in the Verilog stratified event queue model it is guaranteed that an always block >>
is scheduled in the inactive queue in response to an initial clock condition after all propagated initial values have been put into >>
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the active queue. If propagated initial values and triggered always block ever can be in the same queue then order isn't guaranteed >>
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which means that the always block can sample a signal effected by initial values before initial values propagated completely.
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