Likely not. But that example is a particular subtlety of simulation I never noticed! I have to go fix my simulation harness now... :Phttps://twitter.com/oe1cxw/status/892345863254794241 …
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Clock edges at timestamp 0 are especially tricky. I've even seen simulators "optimize away" those edges in some cases (in violation of LRM).
This code with Icarus Verilog: no output. (bug imo) Same code with xsim and modelsim: "ping" Verilator: Did you run with --x-initial-edge?pic.twitter.com/8Z5hiRCWuq
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JFYI, I've now reported the bug in Icarus Verilog: https://github.com/steveicarus/iverilog/issues/160 …
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Oh yeah, that's a race as well: Sim can decide to schedule head of always block (empty block before @(..)) before scheduling the >>
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