Current Status. I admit this can all be very confusing for a beginner. But should I really spend hours of my time giving those answers?pic.twitter.com/cHA6Wm9b17
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What? Is the ordering between declaring a reg and always blocks undefined? Sounds fishy, but haven't checked LRM
Afaik initializations add events directly to the active event queue. So yes, I think this is a race condition.
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You can check the "scheduling semantics" chapter of the LRM.. But whenever I do that I end up being more confused afterwards.. :)
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3.2.2 says reg decl with val should be treated "as if the assignment occurred in a blocking assignment in an initial construct" ...
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