SVA support in Yosys via Verific is coming along nicely. See for example this code that can be processed now:https://github.com/cliffordwolf/yosys/blob/master/tests/sva/counter.sv …
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Also, how does SVA syntax compare to PSL in terms of implementation difficulty / capabilities? Any chance of Yosys PSL support?
No. Only via Verific and only for VHDL. PSL for SystemVerilog is practically dead afaics. (Verific even discontinued PSL/Verilog support.)
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Ah, so SVA is the future? I was distantly looking at both of them, but wasn't sure how widely used either was
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Yes, afaict absolutely. Even many VHDL shops seem to be using SystemVerilog and SVA for formal properties..
End of conversation
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