SVA support in Yosys via Verific is coming along nicely. See for example this code that can be processed now:https://github.com/cliffordwolf/yosys/blob/master/tests/sva/counter.sv …
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Ah, ok. Any chance of seeing native support for SVA in Yosys down the road?
For a certain subset, yes. But don't hold your breadth.. :) But afaik there is no free and open Verilog simulator yet that supports it..
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Also, how does SVA syntax compare to PSL in terms of implementation difficulty / capabilities? Any chance of Yosys PSL support?
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No. Only via Verific and only for VHDL. PSL for SystemVerilog is practically dead afaics. (Verific even discontinued PSL/Verilog support.)
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