TFW someone reports a "Yosys bug" and it turns out it is a 100 MHz design and they did not even bother running timing analysis.
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The perils of software engineers starting into FPGAs?
In many cases. But then please ask a question on stack overflow, don't report "bugs" per email directly to the tool author..
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You've written a really cool tool and are getting new users who never would have agreed to the register to d/l vendor tools
Thanks. Twitter will use this to make your timeline better. UndoUndo
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