TFW someone reports a "Yosys bug" and it turns out it is a 100 MHz design and they did not even bother running timing analysis.
-
Here is an example that actually started on github: https://github.com/cliffordwolf/icestorm/issues/36 … he later sent emails to me and people I work with.
He sent various code snippets but never a complete example and continuously complained to people I work with that I am unfairly ignoring him
-
-
Months later I got a complete example: Turns out he was trying to generate a 250 MHz LVDS signal and he ignored timing analysis results.
-
that's some next level shit
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.