TFW someone reports a "Yosys bug" and it turns out it is a 100 MHz design and they did not even bother running timing analysis.
-
can you just make it policy that every bug report must come with Verilog that reproduces it?
This *IS* the policy. They argue with me that their case is special.. of course.
-
-
i guess that's what the "lock conversation" button there is for
-
Oh, yes! Usually they send me emails, don't use the recommended public channels. Most people who waste my time prefer to do that in private.
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.