TFW someone reports a "Yosys bug" and it turns out it is a 100 MHz design and they did not even bother running timing analysis.
-
.. I even had someone once report a "bug" in a >> 100 MHz design and they ran timing and it said 25 MHz is OK and they just ignored that.
A common pattern here: Those are the bug reports that come with a vague description and a bogus argument why they can't share their code.
-
-
can you just make it policy that every bug report must come with Verilog that reproduces it?
-
This *IS* the policy. They argue with me that their case is special.. of course.
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.