TFW someone reports a "Yosys bug" and it turns out it is a 100 MHz design and they did not even bother running timing analysis.
.. I even had someone once report a "bug" in a >> 100 MHz design and they ran timing and it said 25 MHz is OK and they just ignored that.
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A common pattern here: Those are the bug reports that come with a vague description and a bogus argument why they can't share their code.
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can you just make it policy that every bug report must come with Verilog that reproduces it?
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