.. I even had someone once report a "bug" in a >> 100 MHz design and they ran timing and it said 25 MHz is OK and they just ignored that.
TFW someone reports a "Yosys bug" and it turns out it is a 100 MHz design and they did not even bother running timing analysis.
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A common pattern here: Those are the bug reports that come with a vague description and a bogus argument why they can't share their code.
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It should be impossible to set up an issue on github w/o submitting an MWE to trace down what's happening. Otherwise I would ignore it.
Thanks. Twitter will use this to make your timeline better. UndoUndo
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The perils of software engineers starting into FPGAs?
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In many cases. But then please ask a question on stack overflow, don't report "bugs" per email directly to the tool author..
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