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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. OpenTechLab @opentechlab@mstdn.io‏ @OpenTechLabChan 20 Jul 2017
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      Last year playing with VPR+ice40, I'm unconvinced about it as a PAR for RE'd FPGA bitstreams. Any thoughts for a strategy? @oe1cxw @ico_TC

      2 replies 0 retweets 2 likes
    2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Jul 2017
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      Replying to @OpenTechLabChan @ico_TC

      Same as with ice40: RE and *document* the bitstream first, then find someone to write PAR (or start a new project).

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 21 Jul 2017
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      Replying to @oe1cxw @OpenTechLabChan @ico_TC

      It's much easier to get people onboard when it's about the last missing link to make the flow complete.. :)

      3:27 AM - 21 Jul 2017
      1 reply 0 retweets 0 likes
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        1. OpenTechLab @opentechlab@mstdn.io‏ @OpenTechLabChan 21 Jul 2017
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          Replying to @oe1cxw @ico_TC

          True. People do seem interested in the problem, but noone volunteered to make it happen yet. Hopefully soon

          1 reply 0 retweets 1 like
        2. R. Ou‏ @rqou_ 21 Jul 2017
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          Replying to @OpenTechLabChan @oe1cxw @ico_TC

          We're working on it really really slowly over in ##openfpga on Freenode.

          2 replies 1 retweet 1 like
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