Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

And even with the commercial tools the set of SystemVerilog features supported varies wildly.

They're getting good at the RTL bits these days. always_ff, always_comb, structs, unions, enums all very useful.

Unfortunately the SystemVerilog standard doesn't bother defining which bits are synthesizable..

I think in the long run Verilog will have a more "assembly like" role in most flows. Verilog is absolutely sufficient for that role.

Maybe. I feel someone needs to invent Verilog DWARF first so waveform viewers can annotate actual source.

I think a small standard subset of Verilog + select features from SV would be very useful.

From SV I'd only like immediate assert/assume/restrict/cover, always_comb, and $urandom.

Not concurrent assertions? D: Seriously SVAs are the best.