Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

HEY @oshepherd

Do you like Ada? VHDL. In all other cases, Verilog (preferably SystemVerilog).

There are good open source tools for Verilog (incl. of course my Yosys :). SystemVerilog not so much.

And even with the commercial tools the set of SystemVerilog features supported varies wildly.

They're getting good at the RTL bits these days. always_ff, always_comb, structs, unions, enums all very useful.

Unfortunately the SystemVerilog standard doesn't bother defining which bits are synthesizable..

I think in the long run Verilog will have a more "assembly like" role in most flows. Verilog is absolutely sufficient for that role.