very excite that I have sort of the correct power brick (19V 3.8A but supposed to have 18V 3.48A 
) now I can play with this novena's FPGApic.twitter.com/AERlWeJaic
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Maybe. I feel someone needs to invent Verilog DWARF first so waveform viewers can annotate actual source.
I think a small standard subset of Verilog + select features from SV would be very useful.
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From SV I'd only like immediate assert/assume/restrict/cover, always_comb, and $urandom.
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Not concurrent assertions? D: Seriously SVAs are the best.
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