very excite that I have sort of the correct power brick (19V 3.8A but supposed to have 18V 3.48A 
) now I can play with this novena's FPGApic.twitter.com/AERlWeJaic
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Unfortunately the SystemVerilog standard doesn't bother defining which bits are synthesizable..
I think in the long run Verilog will have a more "assembly like" role in most flows. Verilog is absolutely sufficient for that role.
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Maybe. I feel someone needs to invent Verilog DWARF first so waveform viewers can annotate actual source.
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I think a small standard subset of Verilog + select features from SV would be very useful.
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Most design work will soon be done in higher level languages anyways (like chisel, open cl, whatever is good for the domain).
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I doubt it. HL HW deign has been the coming thing for decades. Did my thesis on it. Verilog and VHDL is what gets stuff done
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