very excite that I have sort of the correct power brick (19V 3.8A but supposed to have 18V 3.48A 
) now I can play with this novena's FPGApic.twitter.com/AERlWeJaic
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They're getting good at the RTL bits these days. always_ff, always_comb, structs, unions, enums all very useful.
Unfortunately the SystemVerilog standard doesn't bother defining which bits are synthesizable..
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Well you know, if you're trying to synthesize a class or a covergroup you're in for a bad time
Thanks. Twitter will use this to make your timeline better. UndoUndo
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I think in the long run Verilog will have a more "assembly like" role in most flows. Verilog is absolutely sufficient for that role.
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Maybe. I feel someone needs to invent Verilog DWARF first so waveform viewers can annotate actual source.
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