very excite that I have sort of the correct power brick (19V 3.8A but supposed to have 18V 3.48A 
) now I can play with this novena's FPGApic.twitter.com/AERlWeJaic
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There are good open source tools for Verilog (incl. of course my Yosys :). SystemVerilog not so much.
And even with the commercial tools the set of SystemVerilog features supported varies wildly.
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They're getting good at the RTL bits these days. always_ff, always_comb, structs, unions, enums all very useful.
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Also, passing multidimensional arrays through ports. Jesus christ Verilog why did you not have that one.
End of conversation
New conversation -
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