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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 15 Jul 2017
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      Replying to @rqou_

      I don't think @efabless is ready to announce prices yet.. But the whole idea is that it's affordable. (Yes, they aren't the foundry.)

      1 reply 0 retweets 0 likes
    2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 15 Jul 2017
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      Replying to @oe1cxw @rqou_ @efabless

      I vaguely remember prices for europractice MPW in large process nodes. They are absolutely within reach for hobby stuff.

      1 reply 0 retweets 0 likes
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 15 Jul 2017
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      Replying to @oe1cxw @rqou_ @efabless

      Oh, europractice actually has their price lists online. No login required: http://www.europractice-ic.com/general_runschedule.php …

      1 reply 1 retweet 2 likes
    4. R. Ou‏ @rqou_ 15 Jul 2017
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      Replying to @oe1cxw

      Oh yeah, @azonenberg told me about that. Still too expensive to regularly make frivolous designs unlike e.g. PCBs

      1 reply 0 retweets 1 like
    5. OSS FPGA & ASIC EDA tools‏ @ico_TC 15 Jul 2017
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      Replying to @rqou_ @oe1cxw @azonenberg

      I am working on that. A set of 10 custom chips should cost the same as a set of 8 layer PCB. So you could run wild with your ideas.

      1 reply 1 retweet 2 likes
    6. 天 Oğuz Meteer 天‏ @BitlogIT 15 Jul 2017
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      Replying to @ico_TC @rqou_ and

      Wait, those prices are in Euros? Some of them are pretty cheap (compared spending millions to billions) 😮

      1 reply 0 retweets 1 like
    7. OSS FPGA & ASIC EDA tools‏ @ico_TC 15 Jul 2017
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      Replying to @BitlogIT @rqou_ and

      To get about 50 chips from a multi project wafer, you need to pay between 8000 and 20000 Euro, depending on node and size of your chip.

      1 reply 1 retweet 2 likes
    8. OSS FPGA & ASIC EDA tools‏ @ico_TC 15 Jul 2017
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      Replying to @ico_TC @BitlogIT and

      This is what IP design companies do to get a "silicon proven" for their IP design. They usually do it several times until the silicon works.

      1 reply 0 retweets 1 like
    9. 天 Oğuz Meteer 天‏ @BitlogIT 16 Jul 2017
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      Replying to @ico_TC @rqou_ and

      The cheapest one I saw was 300 Euros. I'm no expert on chip design, so I don't know if that node is suitable for a mcu, but it's still cheap

      2 replies 0 retweets 0 likes
    10. OSS FPGA & ASIC EDA tools‏ @ico_TC 16 Jul 2017
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      Replying to @BitlogIT @rqou_ and

      It might be 300 Euro per mm². But there might be a minimum order of 25mm².

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 16 Jul 2017
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      Replying to @ico_TC @BitlogIT and

      Minimum order size for ON Semi 0.7µ is 5 mm². But one can also do multi project chips and share that cost.

      5:31 AM - 16 Jul 2017
      1 reply 0 retweets 0 likes
        1. New conversation
        1. 天 Oğuz Meteer 天‏ @BitlogIT 16 Jul 2017
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          Replying to @oe1cxw @ico_TC and

          It literally says "Price/mm^2" in the pdf DOH! I've been misreading things for the last 2 days, I must be tired -_-

          1 reply 0 retweets 1 like
        2. 天 Oğuz Meteer 天‏ @BitlogIT 16 Jul 2017
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          Replying to @BitlogIT @oe1cxw and

          But it is nice that prices are becoming cheaper, and with better EDA tools, a couple of people could actually afford to order custom chips.

          1 reply 0 retweets 1 like
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