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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 7 Jun 2017
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      Flamewar in 3 .. 2 ..pic.twitter.com/FOsX659oc5

      3 replies 2 retweets 7 likes
    2. Andreas Monitzer‏ @anlumo1 7 Jun 2017
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      Replying to @oe1cxw

      Do you think that Verilog is good, not considering the errors in the spec?

      1 reply 0 retweets 0 likes
    3. Dimitar Tomov‏ @tomov_eu 7 Jun 2017
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      Replying to @anlumo1 @oe1cxw

      My view - Choosing between two bad options is never good, but it also means one is worse :D Verilog : VHDL very much seem to be exactly that

      2 replies 1 retweet 0 likes
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      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 8 Jun 2017
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      Replying to @pir_at @tomov_eu @anlumo1

      If I had more time I'd continue my work on Chipy (Constructing Hardware In PYthon).

      12:44 AM - 8 Jun 2017
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      • Dimitar Tomov
      1 reply 0 retweets 1 like
        1. Dimitar Tomov‏ @tomov_eu 8 Jun 2017
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          Replying to @oe1cxw @pir_at @anlumo1

          I know you are dedicated to "new tools" for "new HW", but in my opinion it should be the other way around.

          0 replies 0 retweets 0 likes
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