Oh no you didn't 
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Do you think that Verilog is good, not considering the errors in the spec?
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My view - Choosing between two bad options is never good, but it also means one is worse :D Verilog : VHDL very much seem to be exactly that
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I've always found VHDL delta delays to be it's best feature....
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Hmm :-) I'm a 'long time' C programmer and Verilog is more intuitive for me. C<>MCU& Verilog<>FPGA . 10+ years are considered long, right?
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this is some kind of feedback, it's interesting, the MSc, EE part I did not get though. I know what the abbreviations mean, but MSc 0context
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EE, OK! you are changing/you have changed field, so it's interesting input considering you are coming from High-level Abstractions/Languages
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I understood that, as said earlier. But still I don't get what the MSc has to do with the topic :D Was VHDL promoted in your University or?
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aha, so it started from there. Well, it'd be interesting to see FPGA project from C# VB SQL JAVA person ;- )) It'll be a diff. PoV for sure.
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