Verilator thinks the first one is an abomination, but the second one is fine. Am I missing the obvious clean way to write this code?pic.twitter.com/cV2cYuoWf1
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I sometimes make a module "sign_extend" with parameters for the two widths. Yes, Verilog is awful.
I don't actually think Verilog is awful. Imo my insn_imm_a code is perfectly fine. The problem is that Verilator doesn't think so.
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Ha, I was just looking for ways around this (my x = y is fine and x = {something'd0, y}; does work because widths are configurable). Did you ever find a nice solution?
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doesN'T work ... (I wish Twitter had a temporary edit)
End of conversation
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