Verilator thinks the first one is an abomination, but the second one is fine. Am I missing the obvious clean way to write this code?pic.twitter.com/cV2cYuoWf1
I'd like to get rid of those Verilator warnings, but not at the cost of writing horrible hard-to-read code.
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The Verilator warning msg: %Warning-WIDTH: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS's SIGNED generates 12 bits.
Thanks. Twitter will use this to make your timeline better. UndoUndo
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