I'd like to get rid of those Verilator warnings, but not at the cost of writing horrible hard-to-read code.
Verilator thinks the first one is an abomination, but the second one is fine. Am I missing the obvious clean way to write this code?pic.twitter.com/cV2cYuoWf1
-
-
-
The Verilator warning msg: %Warning-WIDTH: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS's SIGNED generates 12 bits.
- Show replies
New conversation -
-
-
insn_imm_a = `RISCV_FORMAL_XLEN'($signed(rvfi_insn[31:20])); for a subjective definition of cleaner.
-
Cleaner, but it's not Verilog. Unfortunately this type of cast is a SystemVerilog-only feature.
End of conversation
New conversation -
-
-
haven't checked the LRM, but could it be that
$signed is defined to return an integer? Otherwise I'd open a bug. Usually fixed fast -
The return value of
$signed has the same size as the self-sized argument, which is then sign extended to the expression size. - Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.