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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Fiora‏ @FioraAeterna 4 Jun 2017
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      Fiora Retweeted Fabian Giesen

      update: well, shit http://gitweb.dragonflybsd.org/dragonfly.git/commitdiff/b48dd28447fc8ef62fbc963accd301557fd9ac20 …https://twitter.com/rygorous/status/871222539946557440 …

      Fiora added,

      Fabian Giesen @rygorous
      Uh oh. (This is Ryzen, source: https://community.amd.com/message/2796982 ) that's an evil chicken bit to tell people to flip. pic.twitter.com/90Fs65ClgK
      7 replies 28 retweets 54 likes
    2. Fiora‏ @FioraAeterna 4 Jun 2017
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      Replying to @FioraAeterna

      note: this is not actually a particularly bad bug (I mean for one, it has a workaround!), i've shipped worse

      3 replies 3 retweets 48 likes
    3. Fiora‏ @FioraAeterna 4 Jun 2017
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      Replying to @FioraAeterna

      also you really don't want to know just *how many* CPU bugs there are specifically regarding Things That Happen Near Address Space Edges

      4 replies 9 retweets 66 likes
    4. Fiora‏ @FioraAeterna 4 Jun 2017
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      Replying to @FioraAeterna

      it's like the cpu design version of programmers and off-by-one errors

      3 replies 2 retweets 35 likes
    5. Fiora‏ @FioraAeterna 4 Jun 2017
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      Replying to @FioraAeterna

      also i've seen enough "oh, they must have rushed out the chip to have a bug like this!" comments that i have to say this again,pic.twitter.com/M57iiQD1EM

      24 replies 139 retweets 341 likes
    6. Arvid Gerstmann‏ @ArvidGerstmann 4 Jun 2017
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      Replying to @FioraAeterna

      Hardware dev is incredible and frightening. Aren’t their extensive simulations done before releases? Why don’t they catch such bugs?

      3 replies 0 retweets 1 like
    7. Chris Lentini‏ @synulation 4 Jun 2017
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      Replying to @ArvidGerstmann @FioraAeterna

      Extensive testing that catches lots of bugs, but you can never catch them all. Goal is really to produce something viable, not perfect

      1 reply 0 retweets 3 likes
    8. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 4 Jun 2017
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      Replying to @synulation @ArvidGerstmann @FioraAeterna

      That's why you need full end-to-end formal verification against isa spec. My riscv-formal projects aims at providing that for @risc_v CPUs.

      1 reply 2 retweets 4 likes
    9. Erin  ✨ 💽‏ @erincandescent 4 Jun 2017
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      Replying to @oe1cxw @synulation and

      ...Which is fine for ISA-level bugs, but not so for memory system level issues, cache issues, uop cache issues (if present), etc, etc...

      2 replies 0 retweets 2 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Jun 2017
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      Replying to @erincandescent @oshepherd and

      My current riscv-formal models for rocket even include L1 D$ and I$. But yes, in general you want additional proofs for the uncore stuff.

      5:25 AM - 5 Jun 2017
      • 1 Like
      • Muzaffer Kal @🏡 🇺🇸
      0 replies 0 retweets 1 like

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