update: well, shit http://gitweb.dragonflybsd.org/dragonfly.git/commitdiff/b48dd28447fc8ef62fbc963accd301557fd9ac20 …https://twitter.com/rygorous/status/871222539946557440 …
-
Extensive testing that catches lots of bugs, but you can never catch them all. Goal is really to produce something viable, not perfect
That's why you need full end-to-end formal verification against isa spec. My riscv-formal projects aims at providing that for @risc_v CPUs.
-
-
...Which is fine for ISA-level bugs, but not so for memory system level issues, cache issues, uop cache issues (if present), etc, etc...
-
There is no one technique which catches everything, and all tools have fundamental limits
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.