For designs with analog parts a normal event driven or cycle driven dig som will have problems. But that is why we have Spice
TFW someone tells you they don't use test benches "because the design doesn't work in a test bench either". What does that even mean?!
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But in principle - if your rtl does not simulate, you are doing something wrong.
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Another pet peeve: people who use #-delayed assignments in rtl code. It will only guarantee that sim and hw behavior will differentiate
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