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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 22 May 2017
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      Today on "Why isn't​ this crap doing what it's supposed to do!?": This is the "1.2V rail" on this board. I've never seen a hot iCE40 before.pic.twitter.com/z04jZOs3cu

      3 replies 1 retweet 2 likes
    2. Kevin Hubbard‏ @bml_khubbard 22 May 2017
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      Replying to @oe1cxw

      Should have used a Spartan-II apparently !

      1 reply 0 retweets 1 like
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 22 May 2017
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      Replying to @bml_khubbard

      Sometimes its dropping to approx. 1.5V for a few milliseconds. I don't think any part would be happy with this supply rail.

      1 reply 0 retweets 0 likes
    4. Kevin Hubbard‏ @bml_khubbard 22 May 2017
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      Replying to @oe1cxw

      Schematic shows a 5V to 3V buck switcher and then a 3.3V to 1.2V Linear regulator. Are you getting 2.5V on the Switcher output?

      1 reply 0 retweets 0 likes
    5. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 22 May 2017
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      Replying to @bml_khubbard

      I measured 3.3V on the input to the linear regulator (pin 3 on U10). The picture above is directly measured on U10 output (pin 2).

      1 reply 0 retweets 0 likes
    6. Kevin Hubbard‏ @bml_khubbard 22 May 2017
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      Replying to @oe1cxw

      2.5V is a diode drop from 3.3V. I wonder if 3.3V rail is feeding current into a non-existent 1.2V rail via a diode drop inside the FPGA.

      2 replies 0 retweets 0 likes
    7. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 22 May 2017
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      Replying to @bml_khubbard

      I don't think so. I believe the VREG has effectively turned into a diode. But I'll let Trenz figure that out. My job here is done..

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 22 May 2017
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      Replying to @oe1cxw @bml_khubbard

      I don't think so because the FPGA is working "too well". I don't think it would work that well if it be fed parasitically via IO buffers.

      12:38 PM - 22 May 2017
      0 replies 0 retweets 0 likes

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