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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 16 May 2017
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      That's why you need to formal, and then formal your formal. https://github.com/ucb-bar/riscv-torture/issues/11 …pic.twitter.com/GPM5UYeKgb

      3 replies 12 retweets 24 likes
    2. Alastair Reid‏ @alastair_d_reid 17 May 2017
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      Replying to @oe1cxw

      This is a trivial bug for a conventional test suite to find. Formal shines brightest on complex sequences/timings.

      2 replies 0 retweets 1 like
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 May 2017
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      Replying to @alastair_d_reid

      With PicoRV32 it seems I found those problems all with the other formal methods I used before I started my work on riscv-formal.

      1 reply 0 retweets 0 likes
    4. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 May 2017
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      Replying to @oe1cxw @alastair_d_reid

      Essentially comparing the behavior of two PicoRV32 cores (same or different config) on the same memory image but with different timings.

      1 reply 0 retweets 0 likes
    5. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 May 2017
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      Replying to @oe1cxw @alastair_d_reid

      So all the problems that are left here are related to ISA compliance where PicoRV32 consistently was not conforming to the ISA spec.

      1 reply 0 retweets 0 likes
    6. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 May 2017
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      Replying to @oe1cxw @alastair_d_reid

      But the next RISC-V CPU I'll target with riscv-formal is RISC-V Rocket. Big hopes that I'll find more interesting bugs there.

      1 reply 1 retweet 3 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 May 2017
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      Replying to @oe1cxw @alastair_d_reid

      Afaik Rocket hasn't seen any formal yet. Also: Rocket is a 6-stage pipeline. Much more surface for complex bugs to manifest than PicoRV32.

      2:16 AM - 18 May 2017
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      • 天 Oğuz Meteer 天 vincent zimmer Erika OSS FPGA & ASIC EDA tools
      0 replies 1 retweet 3 likes

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