That's why you need to formal, and then formal your formal. https://github.com/ucb-bar/riscv-torture/issues/11 …pic.twitter.com/GPM5UYeKgb
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So all the problems that are left here are related to ISA compliance where PicoRV32 consistently was not conforming to the ISA spec.
But the next RISC-V CPU I'll target with riscv-formal is RISC-V Rocket. Big hopes that I'll find more interesting bugs there.
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Afaik Rocket hasn't seen any formal yet. Also: Rocket is a 6-stage pipeline. Much more surface for complex bugs to manifest than PicoRV32.
Thanks. Twitter will use this to make your timeline better. UndoUndo
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