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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 9 May 2017
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      A sign of significant progress: When the graph is already on a log scale and it still looks like a hockey stick.pic.twitter.com/Spi3FHM9LH

      3 replies 62 retweets 136 likes
    2. Alastair Reid‏ @alastair_d_reid 9 May 2017
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      Replying to @oe1cxw

      I'm routinely throwing expressions of a million operations (64-bit or so) at Z3 and getting answers back in reasonable time. Amazing!

      1 reply 0 retweets 3 likes
    3. OSS FPGA & ASIC EDA tools‏ @ico_TC 9 May 2017
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      Replying to @alastair_d_reid @oe1cxw

      What is reasonable? Over night?

      1 reply 0 retweets 1 like
    4. Alastair Reid‏ @alastair_d_reid 10 May 2017
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      Replying to @ico_TC @oe1cxw

      Almost every true property proved within 1000 seconds. Most proved in under 100. (cex generation seems slow though - couple of hours)

      1 reply 0 retweets 1 like
    5. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 15 May 2017
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      Replying to @alastair_d_reid @ico_TC

      Another perspective: Here is CBMC solving a SAT problem with 113067 vars and 117793 clauses. 20 hours and going..pic.twitter.com/FFbrPJrvCh

      1 reply 0 retweets 0 likes
    6. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 15 May 2017
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      Replying to @oe1cxw @alastair_d_reid @ico_TC

      Tried a different encoding previously that used 3x the numbers of variables. Only took 50 minutes to solve, but also 18 GB memory.

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 15 May 2017
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      Replying to @oe1cxw @alastair_d_reid @ico_TC

      And this is *almost* the same problem. CBMC finished in under 4 minutes. Only about 30 seconds of that spent on solving the SAT instance.pic.twitter.com/4rLaZFA7IT

      11:57 PM - 15 May 2017
      1 reply 0 retweets 0 likes
        1. OSS FPGA & ASIC EDA tools‏ @ico_TC 16 May 2017
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          Replying to @oe1cxw @alastair_d_reid

          VERY nice example!

          0 replies 0 retweets 0 likes
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