Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

And, Verilog (in particular) impedes code reuse as well by having a flat namespace for modules. E.g., if Olof writes a module queue, and >>

>> I write a module queue, then I cannot use both in the same design. I *must* tweak Olof's code or my code to rename modules. Frustrating!

Flat namespaces is one of the things I dislike most about verilog, but C has a similar problem, and they usually handle it with prefixes

Most commercial tools have ways to handle the flat namespace problem and I also have a Yosys feature in the pipeline to deal with that.

Not verilog config statements I hope. That's one of the most confusing things I've seen :)

No. Nobody is using those..

I'll essentially do what everyone else does: structure the design in a hierarchy of workspaces and only make the top module of each ..

.. workspace visible to the workspace one level up in the hierarchy. In the end it's just glorified auto-renaming of modules.