Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

This is something we are working towards with @librecores

I understood that https://ci.librecores.org/  was intended as a tool towards that goal, but there seem to be no manpower available to do it.

Not sure about VHDL, but I do know Verilog itself is a *big* contributor to the problem of community.

Yes. We need to grow our active community to the point where we have the capacity to write tools which can replace our old tools.

And, Verilog (in particular) impedes code reuse as well by having a flat namespace for modules. E.g., if Olof writes a module queue, and >>

>> I write a module queue, then I cannot use both in the same design. I *must* tweak Olof's code or my code to rename modules. Frustrating!

Flat namespaces is one of the things I dislike most about verilog, but C has a similar problem, and they usually handle it with prefixes

Most commercial tools have ways to handle the flat namespace problem and I also have a Yosys feature in the pipeline to deal with that.