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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 7 May 2017
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    Bug found with riscv-formal: PicoRV32 used to incorrectly decode parts of the reserved/unused ISA space as RV32IC insns. This is fixed now.

    12:50 PM - 7 May 2017
    • 4 Retweets
    • 16 Likes
    • 0xdecafbad Nikos Kavvadias vincent zimmer Juan Gonzalez Adam M. Smith Olof Kindgren Alastair Reid Matt 天 Oğuz Meteer 天
    1 reply 4 retweets 16 likes
      1. New conversation
      1. William D. Jones‏ @cr1901 7 May 2017
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        Replying to @oe1cxw

        There's another formal spec project not listed on your github repo readme. But I forget the link right now :/

        1 reply 0 retweets 0 likes
      2. William D. Jones‏ @cr1901 7 May 2017
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        Replying to @cr1901 @oe1cxw

        In any case, Idk if any other project uses it. I find the link tonight...

        0 replies 0 retweets 0 likes
        3. End of conversation

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