Reported three @XilinxInc Vivado bugs with super-simple examples today. Not sure why I'm still doing this.. Code: http://svn.clifford.at/handicraft/2017/vivadobugs …pic.twitter.com/I2iuWCS77P
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In many cases: Auto-generate random Verilog files and use Yosys to verify the results Vivado generates. E.g. http://www.clifford.at/yosys/vloghammer.html …
But in this case I simply re-ran a larger benchmark of "known to be difficult" verilog snippets that I shared with Xilinx years ago.
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Not sure if they fixed the bugs back then, but somehow re-introduced them since then or if they never bothered to fix all bugs exposed by it
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But either way: It is pretty clear that
@XilinxInc has some serious issues with their QA process.. - Show replies
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