Silly "Retro tech" idea of the day: System that takes HDL, sythesises to NAND gates, autoroutes a PCB full of 74HC00's
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Replying to @scanlime @mikelectricstuf
Welp.
@oe1cxw not @clifforwolf . Woops1 reply 0 retweets 1 like -
Didn't
@azonenberg work on something like that using Yosys and KiCad?1 reply 0 retweets 0 likes -
Replying to @oe1cxw @OpenTechLabChan and
I did synthesis of structural Verilog to a KiCAD netlist that was then manually routed. Behavioral would be a fun project though...
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Replying to @azonenberg @OpenTechLabChan and
Well, synthesis of behavioral code to NAND gates is trivial in Yosys. Don't know about KiCad autoplace and autoroute..
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Replying to @oe1cxw @OpenTechLabChan and
You'd still have to pack multiple discrete gates into a 74xx primitive as well. That plus PAR would be interesting.
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Replying to @azonenberg @OpenTechLabChan and
Yes. But packing is very easy if someone else is responsible for writing a PAR tool that has to implement the packed design. :)
10:35 AM - 17 Apr 2017
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