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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Mikes Electric Stuff‏ @mikelectricstuf 17 Apr 2017
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      Silly "Retro tech" idea of the day: System that takes HDL, sythesises to NAND gates, autoroutes a PCB full of 74HC00's

      11 replies 9 retweets 76 likes
    2. OpenTechLab @opentechlab@mstdn.io‏ @OpenTechLabChan 17 Apr 2017
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      Replying to @scanlime @mikelectricstuf

      Welp. @oe1cxw not @clifforwolf . Woops

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 17 Apr 2017
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      Replying to @OpenTechLabChan @scanlime @mikelectricstuf

      Didn't @azonenberg work on something like that using Yosys and KiCad?

      10:08 AM - 17 Apr 2017
      1 reply 0 retweets 0 likes
        1. New conversation
        1. Andrew Zonenberg‏ @azonenberg 17 Apr 2017
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          Replying to @oe1cxw @OpenTechLabChan and

          I did synthesis of structural Verilog to a KiCAD netlist that was then manually routed. Behavioral would be a fun project though...

          1 reply 0 retweets 0 likes
        2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 17 Apr 2017
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          Replying to @azonenberg @OpenTechLabChan and

          Well, synthesis of behavioral code to NAND gates is trivial in Yosys. Don't know about KiCad autoplace and autoroute..

          1 reply 0 retweets 1 like
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