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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. OSS FPGA & ASIC EDA tools‏ @ico_TC 2 Apr 2017
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      First Verilog design synthesized with Yosys and deployed on Cyclone IV! Without any help of @IntelFPGA .pic.twitter.com/5ztu4miOYy

      6 replies 43 retweets 124 likes
    2. 天 Oğuz Meteer 天‏ @BitlogIT 2 Apr 2017
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      Replying to @ico_TC @IntelFPGA

      Wait, there are P&R tools for Alte... Intel now?

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 2 Apr 2017
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      Replying to @BitlogIT @ico_TC @IntelFPGA

      No. This is synthesis with Yosys and P&R with vendor tools.

      5:11 AM - 2 Apr 2017
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      • Charles Goodier (⧖)
      1 reply 1 retweet 1 like
        1. Sergio Cuenca‏ @sergicuen 2 Apr 2017
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          Replying to @oe1cxw @BitlogIT and

          So, Yosys is now a FPGA agnostic synthesis tool, isnt it?

          0 replies 0 retweets 0 likes
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