Xilinx Vivado "write_verilog" output. Why?!? (Yes, this is valid syntax, but I have never seen it used before. Not all tools support it.)pic.twitter.com/gHPQvFHmAu
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What's the purpose of splitting input \^A inside the module's parameter declaration?
this module has no parameter declarations. You'd have to ask @XilinxInc why they chose to declare some module ports like that.
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I meant parameter as in, say, "function/module input/output arguments", b/c I didn't remember the correct term (ports) :).
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I thought so. But jfyi: Verilog modules can also have parameters, and that's a very different thing from a port.
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