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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Mar 2017
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      Xilinx Vivado "write_verilog" output. Why?!? (Yes, this is valid syntax, but I have never seen it used before. Not all tools support it.)pic.twitter.com/gHPQvFHmAu

      3 replies 1 retweet 5 likes
    2. s.t.‏ @stefanct 18 Mar 2017
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      Replying to @oe1cxw

      you don't mean the escaped identifiers i guess...? (My Verilog knowledge is very limited, sorry for the stupid question :)

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Mar 2017
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      Replying to @stefanct

      I mean the .A(....) module port declaration. (escaped identifiers are pretty common.)

      8:53 AM - 18 Mar 2017
      1 reply 0 retweets 0 likes
        1. s.t.‏ @stefanct 18 Mar 2017
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          Replying to @oe1cxw

          thanks, figured it out after reading @cr1901's message. i did not pay attention to the components of the port itself, weird :)

          0 replies 0 retweets 0 likes
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