Xilinx Vivado "write_verilog" output. Why?!? (Yes, this is valid syntax, but I have never seen it used before. Not all tools support it.)pic.twitter.com/gHPQvFHmAu
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Thanks. Twitter will use this to make your timeline better. UndoUndo
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you don't mean the escaped identifiers i guess...? (My Verilog knowledge is very limited, sorry for the stupid question :)
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I mean the .A(....) module port declaration. (escaped identifiers are pretty common.)
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What's the purpose of splitting input \^A inside the module's parameter declaration?
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this module has no parameter declarations. You'd have to ask
@XilinxInc why they chose to declare some module ports like that. - Show replies
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