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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Andrew Zonenberg‏ @azonenberg 15 Mar 2017
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      Seeking papers on netlist-to-HDL / netlist-to-semantics analysis. Anybody doing work in the field / know of good publications?

      2 replies 3 retweets 1 like
    2. Eric LaForest‏ @elaforest 15 Mar 2017
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      Replying to @azonenberg

      Maybe @oe1cxw would know?

      1 reply 0 retweets 1 like
    3. Andrew Zonenberg‏ @azonenberg 15 Mar 2017
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      Replying to @elaforest @oe1cxw

      Pretty much undoing synthesis, so related...

      1 reply 0 retweets 1 like
    4. OSS FPGA & ASIC EDA tools‏ @ico_TC 15 Mar 2017
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      Replying to @azonenberg @elaforest @oe1cxw

      Clifford wrote a bitstream-to-verlilog tool for the ice40.

      1 reply 0 retweets 1 like
    5. Andrew Zonenberg‏ @azonenberg 15 Mar 2017
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      Replying to @ico_TC @elaforest @oe1cxw

      There's a big difference between "a bunch of Verilog LUT primitives" and "full behavioral HDL w/ hierarchy etc"

      2 replies 0 retweets 1 like
    6. Eric LaForest‏ @elaforest 16 Mar 2017
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      Replying to @azonenberg @ico_TC @oe1cxw

      Not sure that's possible: no indication of when signals cross a module boundary, unlike function calls.

      3 replies 0 retweets 1 like
    7. Andrew Zonenberg‏ @azonenberg 16 Mar 2017
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      Replying to @elaforest @ico_TC @oe1cxw

      I expected hierarchy would be somewhat manually guided based on a human's assessment.

      1 reply 0 retweets 1 like
    8. Andrew Zonenberg‏ @azonenberg 16 Mar 2017
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      Replying to @azonenberg @elaforest and

      Goal is the "silicon IDA"

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 16 Mar 2017
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      Replying to @azonenberg @elaforest @ico_TC

      a few years ago I made some experiments in that direction based on 6502 transistor-level netlists

      9:38 AM - 16 Mar 2017
      1 reply 0 retweets 0 likes
        1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 16 Mar 2017
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          Replying to @oe1cxw @azonenberg and

          http://svn.clifford.at/handicraft/2013/logic6502/ …

          0 replies 0 retweets 1 like
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