Maybe @oe1cxw would know?
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Replying to @elaforest @oe1cxw
Pretty much undoing synthesis, so related...
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Clifford wrote a bitstream-to-verlilog tool for the ice40.
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There's a big difference between "a bunch of Verilog LUT primitives" and "full behavioral HDL w/ hierarchy etc"
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Not sure that's possible: no indication of when signals cross a module boundary, unlike function calls.
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Replying to @elaforest @azonenberg and
Interesting! Maybe heuristic of equiv classes of like-prims and bottom up hash consing => poly time
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Replying to @jangray @elaforest and
used a similar technique once to fold and dedup cyclic graphs of types in
@visualc debug info linking1 reply 0 retweets 2 likes -
Replying to @jangray @elaforest and
canonicalize LUT truth tables under pin rearrangement?
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Replying to @jangray @elaforest and
doesn't help with topologically different mappings of functions to more than one LUT
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the only known canonical representation afaik is BDDs, but it's worst case exponential in space
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and even BDDs don't help much for sub-circuit extraction
9:19 AM - 16 Mar 2017
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