Seeking papers on netlist-to-HDL / netlist-to-semantics analysis. Anybody doing work in the field / know of good publications?
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Replying to @elaforest @oe1cxw
Pretty much undoing synthesis, so related...
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Clifford wrote a bitstream-to-verlilog tool for the ice40.
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There's a big difference between "a bunch of Verilog LUT primitives" and "full behavioral HDL w/ hierarchy etc"
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Not sure that's possible: no indication of when signals cross a module boundary, unlike function calls.
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one could try to extract max isomorphic subgraphs or equivalent subcircuits. I think both are PSPACE complete
7:38 AM - 16 Mar 2017
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