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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Mar 2017
      • Report Tweet
      • Report NetzDG Violation

      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩 Retweeted Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

      Hint: The answer is in my recent github activity.https://twitter.com/oe1cxw/status/838460444637548544 …

      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩 added,

      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩 @oe1cxw
      One billion internet points for anyone who figures out what this notes are. Hint: Some of my followers might have made quite similar notes. pic.twitter.com/YitbjpXgiY
      1 reply 1 retweet 1 like
    2. Richard Maxwell‏ @JodiTheTigger 5 Mar 2017
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      Replying to @oe1cxw

      ok, ill bite. It's the mapping of RISC-V asm to x86 mov op codes!

      1 reply 0 retweets 1 like
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Mar 2017
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      Replying to @JodiTheTigger

      getting warmer!

      1 reply 0 retweets 0 likes
    4. Richard Maxwell‏ @JodiTheTigger 5 Mar 2017
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      Replying to @oe1cxw

      Oooh. If it's RISCV based, then maybe something do to with decoding RISCV instructions?

      1 reply 0 retweets 1 like
    5. std::vector‏ @_nihilant_ 5 Mar 2017
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      Replying to @JodiTheTigger @oe1cxw

      Immediate decoding for RV 15-bit instructions.

      2 replies 1 retweet 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 5 Mar 2017
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      Replying to @_nihilant_ @JodiTheTigger

      on a 2nd read: 15-bit? what happened to the last bit? ;)

      1:41 PM - 5 Mar 2017
      1 reply 0 retweets 0 likes
        1. std::vector‏ @_nihilant_ 5 Mar 2017
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          Replying to @oe1cxw @JodiTheTigger

          ups :P

          0 replies 0 retweets 1 like
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