Without anyone reporting a bug about it? Nice! Normally you'd have to harass a company for years before they look into it.
just found a 2nd bug in the same frickin line! https://github.com/cliffordwolf/yosys/commit/c449f4b86f66ca4ef2396454f09a73d56ff06512 …https://twitter.com/oe1cxw/status/830358377175846913 …
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some formal proofs that work with Yosys' native Verilog front-end failed when using verific as front-end.
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I only got a build of a verific lib with initialization support today. Before that this code was never executed.
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