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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 6 Feb 2017
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      Does anyone have a simple VHDL project with formal safety properties that I could use as test case for Yosys+Verific+SymbiYosys?

      1 reply 9 retweets 2 likes
    2. Olof Kindgren‏ @OlofKindgren 6 Feb 2017
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      Replying to @oe1cxw

      If you're looking for something as simple as a FIFO, I got it here https://github.com/olofk/libstorage …

      1 reply 0 retweets 0 likes
    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 6 Feb 2017
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      Replying to @OlofKindgren

      I don't see any formal properties. Am I missing something?

      1 reply 0 retweets 0 likes
    4. Olof Kindgren‏ @OlofKindgren 6 Feb 2017
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      Replying to @oe1cxw

      Oh, sorry. Just thought you wanted something that could easily be formally verified

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 6 Feb 2017
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      Replying to @OlofKindgren

      might still be a good starting point, if I figure out the syntax for safety properties in VHDL.. not many examples online.

      12:32 PM - 6 Feb 2017
      1 reply 0 retweets 0 likes
        1. New conversation
        1. Olof Kindgren‏ @OlofKindgren 6 Feb 2017
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          Replying to @oe1cxw

          Safety properties == PSL? I used to do formal verification of VHDL with PSL ~10 years ago

          1 reply 0 retweets 0 likes
        2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 7 Feb 2017
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          Replying to @OlofKindgren

          PSL would be one way. assert/assume in processes another. I'm now testing with this example using PSL that I found online.pic.twitter.com/MNrljwuAa2

          2 replies 0 retweets 0 likes
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