Does anyone have a simple VHDL project with formal safety properties that I could use as test case for Yosys+Verific+SymbiYosys?
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If you're looking for something as simple as a FIFO, I got it here https://github.com/olofk/libstorage …
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Oh, sorry. Just thought you wanted something that could easily be formally verified
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might still be a good starting point, if I figure out the syntax for safety properties in VHDL.. not many examples online.
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